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74LVT32374 * 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
April 2001 Revised June 2002
74LVT32374 * 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The LVT32374 and LVTH32374 contain thirty-two noninverting D-type flip-flops with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and Output Enable (OE) are common to each byte and can be shorted together for full 32-bit operation. The LVTH32374 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32374 and LVTH32374 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32374) s Also available without bushold feature (74LVT32374) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT32374G (Note 1)(Note 2) 74LVTH32374G (Note 1)(Note 2) Package Number BGA96A (Preliminary) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2002 Fairchild Semiconductor Corporation
DS500452
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74LVT32374 * 74LVTH32374
Connection Diagram
Pin Descriptions
Pin Names OEn CPn I0-I31 O0-O31 Description Output Enable Input (Active LOW) Clock Pulse Input Inputs 3-STATE Outputs
FBGA Pin Assignments
1 A B C D E F G H (Top Thru View) J K L M N P R T O1 O3 O5 O7 O9 O11 O13 O14 O17 O19 O21 O23 O25 O27 O29 O30 2 O0 O2 O4 O6 O8 O10 O12 O15 O16 O18 O20 O22 O24 O26 O28 O31 3 OE1 GND VCC1 GND GND VCC1 GND OE2 OE3 GND VCC2 GND GND VCC2 GND OE4 4 CP1 GND VCC1 GND GND VCC1 GND CP2 CP3 GND VCC2 GND GND VCC2 GND CP4 5 I0 I2 I4 I6 I8 I10 I12 I15 I16 I18 I20 I22 I24 I26 I28 I31 6 I1 I3 I5 I7 I9 I11 I13 I14 I17 I19 I21 I23 I25 I27 I29 I30
Functional Description
The LVT32374 and LVTH32374 consist of thirty-two edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 32-bit operation. Each byte has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each flip-flop will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CPn) transition. With the Output Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operation of the OEn input does not affect the state of the flip-flops.
Truth Tables
Inputs CP1 Outputs I0-I7 H L X X O0-O7 H L Oo Z Outputs I16-I23 H L X X O16-O23 H L Oo Z CP4 CP2 Inputs Outputs I8-I15 H L X X O8-O15 H L Oo Z Outputs I24-I31 H L X X O24-O31 H L Oo Z

L X
OE1 L L L H Inputs

L X
OE2 L L L H Inputs
CP3

L X
OE3 L L L H

L X
OE4 L L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
Z = HIGH Impedance Oo = Previous Oo before HIGH-to-LOW of CP
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74LVT32374 * 74LVTH32374
Logic Diagrams
Byte 1 (0:7)
Byte 2 (8:15)
Byte 3 (16:23)
Byte 4 (24:31)
VCC1 is associated with Bytes 1 and 2. VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided for the understanding of logic operation and should not be used to estimate propagation delays.
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74LVT32374 * 74LVTH32374
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-32
64
-40
0
85 10
C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ Power Off Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.0 Bushold Input Minimum Drive 3.0 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 A A A A A A VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 A A V V 2.0 0.8 T A = -40C to +85C Min Max -1.2 Units V V V Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.5V VO = 3.0V VCC < VO 5.5V
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74LVT32374 * 74LVTH32374
DC Electrical Characteristics
Symbol ICCH ICCL ICCZ ICCZ+ ICC Parameter Power Supply Current Power Supply Current Power Supply Current Power Supply Current
(Continued)
VCC (V) T A = -40C to +85C Min Max 0.19 5 0.19 0.19 mA mA mA mA Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Units
Conditions
(VCC1 or VCC2) (VCC1 or VCC2) (VCC1 or VCC2) (VCC1 or VCC2)
3.6 3.6 3.6 3.6
Increase in Power Supply Current (VCC1 or VCC2) (Note 8)
3.6
0.2
mA
Note 5: Applies to bushold version only (74LVTH32374). Note 6: An external driver must sink at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 Min
(Note 9)
TA = 25C Typ 0.8 -0.8 Max Units V V Conditions CL = 50 pF, RL = 500 (Note 10) (Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C, CL = 50 pF, RL = 500 Symbol Parameter VCC = 3.3V 0.3V Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tS tH tW Setup Time Hold Time Pulse Width Output Disable Time Maximum Clock Frequency Propagation Delay CP to On Output Enable Time 160 1.9 1.6 1.3 1.0 1.5 2.0 1.8 0.8 3.0 4.3 4.5 4.4 4.5 4.6 5.0 Max 160 1.9 1.6 1.3 1.0 1.5 2.0 2.0 0.1 3.0 4.6 5.2 5.0 5.4 4.8 5.4 VCC = 2.7V Min Max MHz ns ns ns ns ns ns Units
Capacitance (Note 11)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VCC = OPEN, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT32374 * 74LVTH32374 Low Voltage 32-Bit D-Type Flip-Flop with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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